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19-3595; Rev 0; 2/05
KIT ATION EVALU ABLE AVAIL
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
General Description Features
Eight (MAX6889), Six (MAX6890), or Four (MAX6891) Configurable Input Voltage Detectors High-Voltage Input (1.25V to 7.625V or 2.5V to 13.2V) Six (MAX6889), Five (MAX6890), or Three (MAX6891) Voltage Inputs (0.5V to 3.05V or 1V to 5.5V) Additional (MAX6889) High-Voltage Input (1.25V to 7.625V or 2.5V to 15.25V) Four (MAX6889/MAX6890) or Three (MAX6891) General-Purpose Logic Inputs Configurable Watchdog Timer Ten (MAX6889), Eight (MAX6890), or Five (MAX6891) Programmable Outputs Active-High, Active-Low, Open Drain, Weak Pullup Timing Delays from 25s to 1600ms Margining Disable and Manual Reset Controls 512-Bit Internal User EEPROM Endurance: 100,000 Erase/Write Cycles Data Retention: 10 Years I2C/SMBus-Compatible Serial Configuration/Communication Interface 1% Threshold Accuracy
MAX6889/MAX6890/MAX6891
The MAX6889/MAX6890/MAX6891 EEPROM-configurable, multivoltage supply sequencers/supervisors monitor several voltage detector inputs and generalpurpose logic inputs and feature programmable outputs for highly configurable power-supply sequencing applications. The MAX6889 features eight voltage detector inputs and ten programmable outputs. The MAX6890 features six voltage detector inputs and eight programmable outputs, while the MAX6891 features four voltage detector inputs and five programmable outputs. Manual reset and margin disable inputs offer additional flexibility. All voltage detectors offer a configurable threshold for undervoltage detection. High-voltage input IN1 monitors voltages from 2.5V to 13.2V in 50mV increments, or from 1.25V to 7.625V in 25mV increments. Inputs IN2-IN7 monitor voltages from 1V to 5.5V in 20mV increments or from 0.5V to 3.05V in 10mV increments. High-voltage input IN8 monitors voltages from 2.5V to 15.25V in 50mV increments, or from 1.25V to 7.625V in 25mV increments. Programmable output stages control power-supply sequencing or system resets/interrupts. Programmable output options include: active-high, active-low, open drain, and weak pullup. Programmable timing delay blocks configure each output to wait between 25s and 1600ms before deasserting. The MAX6889/MAX6890/MAX6891 feature a watchdog timer for added flexibility. Program the watchdog timer to assert one or more programmable outputs. The initial and normal watchdog timeout periods are independently programmable from 6.25ms to 102.4s. An SMBusTM/I2C*-compatible, 2-wire serial data interface programs and communicates with the configuration EEPROM, the configuration registers, and the internal 512-bit user EEPROM. The MAX6889/MAX6890/MAX6891 are available in 5mm x 5mm x 0.8mm thin QFN packages and are specified to operate over the extended temperature range (-40C to +85C).
Ordering Information
PART MAX6889ETJ MAX6890ETI MAX6891ETP TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 32 Thin QFN 28 Thin QFN 20 Thin QFN PKG CODE T3255-4 T2855-8 T2055-5
Applications
Telecommunication/Central Office Systems Networking Systems Servers/Workstations Base Stations Storage Equipment Multi-Microprocessor/Voltage Systems
Pin Configurations and Typical Operating Circuit appear at end of data sheet.
SMBus is a trademark of Intel Corp. *Purchase of I2C components from Maxim Integrated Products, Inc. or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) IN2-IN7, VCC, SDA, SCL, A0, A1, GPI_ MR, MARGIN .........................................................-0.3V to +6V IN1, PO_ .................................................................-0.3V to +14V IN8 ..........................................................................-0.3V to +20V DBP ..........................................................................-0.3V to +3V Input/Output Current (all pins)..........................................20mA Continuous Power Dissipation (TA = +70C) 20-Pin Thin QFN (derate 21.3mW/C above +70C)..............................................................1702mW 28-Pin Thin QFN (derate 21.3mW/C above +70C)..............................................................1702mW 32-Pin Thin QFN (derate 21.3mW/C above +70C)..............................................................1702mW Operating Temperature Range ...........................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN1 = 6.5V to 13.2V, VIN2-VIN7 = 2.7V to 5.5V, VIN8 = 10V, GPI_ = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2, 3)
PARAMETER SYMBOL VIN1 Operating Voltage Range (Note 4) CONDITIONS Voltage on IN1 to ensure the device is fully operational, IN2-IN8 = GND Voltage on any one of IN2-IN5 or VCC to ensure the device is fully operational, IN1 = GND VIN1P Minimum voltage on IN1 to guarantee that the device is powered through IN1 Minimum voltage on one of IN2-IN5 to guarantee the device is EEPROM configured No load VIN1 = 13.2V, IN2-IN8 = GND, no load Supply Current ICC Writing to configuration registers or EEPROM, no load VIN1 (50mV increments) VIN1 (25mV increments) VIN2-VIN7 (20mV increments) Threshold Voltage Range VTH VIN2-VIN7 (10mV increments) VIN8 (50mV increments) VIN8 (25mV increments) VIN2-VIN8 (high-Z mode in 3.3mV increments) 2.5 1.25 1.0 0.50 2.50 1.250 0.167 2.48 2.55 1 1.1 MIN 4.0 TYP MAX 13.2 V 2.7 5.5 UNITS
IN1 Supply Voltage (Note 4)
6.5
V
Undervoltage Lockout Digital Bypass Voltage
VUVLO VDBP
2.5 2.67 1.2 1.5 13.2 7.625 5.5 3.05 15.25 7.625 1.017
V V mA mA
V
2
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = 6.5V to 13.2V, VIN2-VIN7 = 2.7V to 5.5V, VIN8 = 10V, GPI_ = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2, 3)
PARAMETER SYMBOL CONDITIONS VIN_ = 2.5V to 5.5V (20mV increments) TA = +25C to +85C (VIN_ falling) VIN_ = 1V to 2.5V (20mV increments) VIN_ = 1.25V to 3.05V (10mV increments) VIN_ = 0.5V to 1.25V (10mV increments) VIN_ = 2.5V to 5.5V (20mV increments) TA = -40C to +85C (VIN_ falling) VIN_ = 1V to 2.5V (20mV increments) VIN_ = 1.25V to 3.05V (10mV increments) VIN_ = 0.5V to 1.25V (10mV increments) VIN_ = 6.25V to 13.2V (6.25V to 15.25V for IN8) (50mV increments) TA = +25C to +85C (VIN_ falling) VIN_ = 2.5V to 6.25V (50mV increments) VIN_ = 3.125V to 7.625V (25mV increments) VIN_ = 1.25V to 3.125V (25mV increments) IN1/IN8 Threshold Accuracy VIN_ = 6.25V to 13.2V (6.25V to 15.25V for IN8) (50mV increments) TA = -40C to +85C (VIN_ falling) VIN_ = 2.5V to 6.25V (50mV increments) VIN_ = 3.125V to 7.625V (25mV increments) VIN_ = 1.25V to 3.125V (25mV increments) IN_ Threshold Accuracy Threshold Hysteresis VTH-HYST IN_ = 0.6V in high-Z mode (VIN_ falling) TA = +25C to +85C TA = -40C to 85C MIN -1 -25 -1 -12.5 -2 -50 -2 -25 TYP MAX +1 +25 +1 +12.5 +2 +50 +2 +25 UNITS % mV % mV % mV % mV
MAX6889/MAX6890/MAX6891
IN2-IN7 Threshold Accuracy
-1
+1
%
-62.5 -1 -31.25
+62.5 +1 +31.25
mV % mV
-2
+2
%
-125
+125
mV
-2
+2
%
-62.5 -1 -2 0.3
+62.5 +1 +2
mV
% % VTH
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3
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = 6.5V to 13.2V, VIN2-VIN7 = 2.7V to 5.5V, VIN8 = 10V, GPI_ = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2, 3)
PARAMETER Reset-Threshold Temperature Coefficient Threshold-Voltage Differential Nonlinearity IN1 Input Leakage Current IN2-IN7 Input Impedance IN8 Input Impedance IN2-IN8 Input Leakage Current Power-Up Delay IN_ to PO_ Delay SYMBOL VTH/C VTH DNL ILIN1 For VIN1 < the highest of VIN2-VIN5 290 730 -50 20 25 1.406 5.625 22.5 45 180 360 1440 1.5625 6.25 25 50 200 400 1600 1.719 6.875 27.5 55 220 440 1760 0.4 10 -1 6.6 1.4 1 100 tDMR IMR IMARGIN tDGPI_ IGPI_ tWDI VGPI_ = 0.6V GPI_ configured as a watchdog input 5 50 VMR = 1.4V VMARGIN = 1.4V 5 5 2 10 10 100 200 10 15 15 15 10 40 +1 15.0 0.6 V A A k V s ns s A A mV ns A ns ms -1 100 400 1000 CONDITIONS MIN TYP 10 +1 140 555 1400 +50 3 000 001 010 PO_ Timeout Period tRP Register contents (Table 19) 011 100 101 110 111 PO_ Output Low PO_ Output Initial Pulldown Current PO_ Output Open-Drain Leakage Current PO_ Output Pullup Resistance MR, MARGIN, GPI_ Input Voltage MR Input Pulse Width MR Glitch Rejection MR to PO_ Delay MR to DBP Pullup Current MARGIN to DBP Pullup Current GPI_ Input Hysteresis GPI_ to PO_ Delay GPI_ Pulldown Current Watchdog Input Pulse Width VOL IPD ILKG RPU VIL VIH tMR ISINK = 4mA, output asserted VCC < VUVLO, VPO = 0.8V Output high impedance VPO_ = 2V MAX UNITS ppm/C LSB A k k nA ms s s
RIN2 to RIN7 VIN1 > 6.5V RIN8 ILIN2-LIN8 tPU tDPO IN2-IN8 in high-Z mode, VIN_ = 1.017V VCC > VUVLO VIN_ falling or rising, 100mV overdrive
4
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = 6.5V to 13.2V, VIN2-VIN7 = 2.7V to 5.5V, VIN8 = 10V, GPI_ = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2, 3)
PARAMETER SYMBOL CONDITIONS 000 001 010 Watchdog Timeout Period tWD Register contents (Table 21) 011 100 101 110 111 SERIAL INTERFACE LOGIC (SDA, SCL, A0, A1) Logic-Input Low Voltage Logic-Input High Voltage Input Leakage Current Output Low Voltage Input/Output Capacitance VIL VIH ILKG VOL CI/O ISINK = 3mA 10 2.0 -1 +1 0.4 0.8 V V A V pF MIN 5.625 22.5 90 360 1.44 5.76 23.04 92.16 TYP 6.25 25 100 400 1.60 6.40 25.60 102.40 MAX 6.875 27.5 110 440 1.76 7.04 28.16 112.64 s ms UNITS
MAX6889/MAX6890/MAX6891
SERIAL INTERFACE TIMING CHARACTERISTICS (Figure 3)
(IN1 = GND, VIN2-VIN7 = 2.7V to 5.5V, VIN8 = 10V, GPI_ = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2, 3)
PARAMETER Serial Clock Frequency Clock Low Period Clock High Period Bus-Free Time START Setup Time START Hold Time STOP Setup Time Data In Setup Time Data In Hold Time Receive SCL/SDA Minimum Rise Time Receive SCL/SDA Maximum Rise Time Receive SCL/SDA Minimum Fall Time Receive SCL/SDA Maximum Fall Time Transmit SDA Fall Time SYMBOL fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR tR tF tF tF (Note 5) (Note 5) (Note 5) (Note 5) CBUS = 400pF 20 + 0.04 x CBUS 1.3 0.6 1.3 0.6 0.6 0.6 100 30 20 + 0.1 x CBUS 300 20 + 0.1 x CBUS 300 300 900 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s s s ns ns ns ns ns ns ns
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5
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
SERIAL INTERFACE TIMING CHARACTERISTICS (Figure 3) (continued)
(IN1 = GND, VIN2-VIN7 = 2.7V to 5.5V, VIN8 = 10V, GPI_ = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2, 3)
PARAMETER Pulse Width of Spike Suppressed EEPROM Byte Write Cycle Time SYMBOL tSP tWR (Note 6) (Note 7) CONDITIONS MIN TYP 50 11 MAX UNITS ns ms
Note 1: 100% production tested at TA = +25C and TA = +85C. Specifications at TA = -40C are guaranteed by design. Note 2: Specifications are guaranteed for the stated global conditions. The device also meets the parameters specified when 0 < VIN1 < 6.5V and at least one of VIN2-VIN5 is between 2.7V and 5.5V, while the remaining VIN2-VIN5 are between 0 and 5.5V. Specifications are also guaranteed if VCC is externally supplied. Note 3: Device may be supplied from any one of IN1 to IN5, or VCC (see the Powering the MAX6889/MAX6890/MAX6891 section). Note 4: The internal supply voltage, measured at VCC, equals the maximum of IN2 to IN5 if VIN1 = 0V, or equals 5.4V if VIN1 > 6.5V. For 4V < VIN1 < 6.5V and VIN2-VIN5 > 2.7V, the input that powers the device cannot be determined. Note 5: CBUS = total capacitance of one bus line in pF. Rise and fall times are measured between 0.1 x VBUS and 0.9 x VBUS. Note 6: Input filters on SDA, SCL, A0, and A1 suppress noise spikes < 50ns. Note 7: An additional cycle is required when writing to configuration memory for the first time.
Typical Operating Characteristics
(VIN1 = 6.5V to 13.2V, VIN8 = 10V, VIN_ = 2.7V to 5.5V, GPI_ = GND, MARGIN = MR = DBP, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (IN1)
MAX6889 toc01
SUPPLY CURRENT vs. SUPPLY VOLTAGE (IN2-IN5)
MAX6889 toc02
NORMALIZED PO_ TIMEOUT PERIOD vs. TEMPERATURE
NORMALIZED PO_ TIMEOUT PERIOD
MAX6889 toc03
1.3 1.2 SUPPLY CURRENT (mA) 1.1 1.0 TA = +25C 0.9 0.8 0.7 6.5 7.5 8.5 9.5 10.5 11.5 12.5 TA = -40C TA = +85C
1.2 1.1 SUPPLY CURRENT (mA) 1.0 0.9 TA = +25C 0.8 0.7 0.6 TA = -40C TA = +85C
1.3 1.2 1.1 1.0 0.9 0.8 0.7
13.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
6
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Typical Operating Characteristics (continued)
(VIN1 = 6.5V to 13.2V, VIN8 = 10V, VIN_ = 2.7V to 5.5V, GPI_ = GND, MARGIN = MR = DBP, TA = +25C, unless otherwise noted.)
IN_ TO PO_ PROPAGATION DELAY vs. TEMPERATURE
MAX6889 toc04
NORMALIZED WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE
MAX6889 toc05
NORMALIZED IN_ THRESHOLD vs. TEMPERATURE
1.004 NORMALIZED IN_ THRESHOLD 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995
MAX6889 toc06
30 IN_ TO PO_ PROPAGATION DELAY (s) 28 26 24 22 20 18 16 14 12 10
NORMALIZED WATCHDOG TIMEOUT PERIOD
100mV OVERDRIVE
1.020 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0.980 -40 -15 10 35 60
1.005
-40
-15
10
35
60
85
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
MAXIMUM IN_ TRANSIENT vs. IN_ THRESHOLD OVERDRIVE
MAX6889 toc07
OUTPUT VOLTAGE LOW vs. SINK CURRENT
MAX6889 toc08
OUTPUT VOLTAGE HIGH vs. SOURCE CURRENT
2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.04 0.08 0.12 IOUT (mA) WEAK PULLUP
MAX6889 toc09
200 MAXIMUM TRANSIENT DURATION (s) 175 150
500 450 400 350
100 75 50 25 0 1 10 100 1000 IN_ THRESHOLD OVERDRIVE (mV) PO_ ASSERTION OCCURS ABOVE THIS LINE
250 200 150 100 50 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ISINK (mA)
VOH (mV)
VOL (mV)
125
300
0.16
0.20
0.24
MR TO PO_ PROPAGATION DELAY vs. TEMPERATURE
MR TO PO_ PROPAGATION DELAY (s) 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 -40 -15 10 35 60 85 TEMPERATURE (C)
MAX6889 toc10
2.20
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7
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Pin Description
PIN MAX6889 MAX6890 MAX6891 NAME FUNCTION Programmable Output 2. Configurable, active-high, active-low, open-drain, or weak pullup output. PO2 pulls low with a 10A internal current sink for 1V < VCC < VUVLO. PO2 assumes its programmed conditional output state when VCC exceeds undervoltage lockout (UVLO) of 2.5V. Programmable Output 3. Configurable, active-high, active-low, open-drain, or weak pullup output. PO3 pulls low with a 10A internal current sink for 1V < VCC < VUVLO. PO3 assumes its programmed conditional output state when VCC exceeds undervoltage lockout (UVLO) of 2.5V. Programmable Output 4. Configurable, active-high, active-low, open-drain, or weak pullup output. PO4 pulls low with a 10A internal current sink for 1V < VCC < VUVLO. PO4 assumes its programmed conditional output state when VCC exceeds undervoltage lockout (UVLO) of 2.5V. Ground Programmable Output 5. Configurable, active-high, active-low, open-drain, or weak pullup output. PO5 pulls low with a 10A internal current sink for 1V < VCC < VUVLO. PO5 assumes its programmed conditional output state when VCC exceeds undervoltage lockout (UVLO) of 2.5V. Programmable Output 6. Configurable, active-high, active-low, open-drain, or weak pullup output. PO6 pulls low with a 10A internal current sink for 1V < VCC < VUVLO. PO6 assumes its programmed conditional output state when VCC exceeds undervoltage lockout (UVLO) of 2.5V. Programmable Output 7. Configurable, active-high, active-low, open-drain, or weak pullup output. PO7 pulls low with a 10A internal current sink for 1V < VCC < VUVLO. PO7 assumes its programmed conditional output state when VCC exceeds undervoltage lockout (UVLO) of 2.5V. Programmable Output 8. Configurable, active-high, active-low, open-drain, or weak pullup output. PO8 pulls low with a 10A internal current sink for 1V < VCC < VUVLO. PO8 assumes its programmed conditional output state when VCC exceeds undervoltage lockout (UVLO) of 2.5V. Programmable Output 9. Configurable, active-high, active-low, open-drain, or weak pullup output. PO9 pulls low with a 10A internal current sink for +1V < VCC < VUVLO. PO9 assumes its programmed conditional output state when VCC exceeds undervoltage lockout (UVLO) of 2.5V. Programmable Output 10. Configurable, active-high, active-low, open-drain, or weak pullup output. PO10 pulls low with a 10A internal current sink for 1V < VCC < VUVLO. PO10 assumes its programmed conditional output state when VCC exceeds undervoltage lockout (UVLO) of 2.5V. Margin Input. MARGIN holds PO_ in its existing state when MARGIN is driven low. Leave MARGIN unconnected or connect to DBP if unused. MARGIN overrides MR if both assert at the same time. MARGIN is internally pulled up to DBP through a 10A current source.
1
1
1
PO2
2
2
2
PO3
3
3
3
PO4
4
4
4
GND
5
5
5
PO5
6
6
--
PO6
7
7
--
PO7
8
8
--
PO8
9
--
--
PO9
10
--
--
PO10
11
9
6
MARGIN
8
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
Pin Description (continued)
PIN MAX6889 MAX6890 MAX6891 NAME FUNCTION Manual Reset Input. MR is configurable to either assert PO_ into a programmed state or to have no effect on PO_ when driving MR low (see Table 6). Leave MR unconnected or connect to DBP if unused. MR is internally pulled up to DBP through a 10A current source. Serial Data Input/Output (Open Drain). SDA requires an external pullup resistor. Serial Clock Input. SCL requires an external pullup resistor. Address Input 0. Address inputs allow up to four (MAX6889/MAX6890) or two (MAX6891) connections on one common bus. Connect A0 to GND or to the serial-interface power supply. Address Input 1. Address inputs allow up to four MAX6889/MAX6890 connections on one common bus. Connect A1 to GND or to the serial-interface power supply. General-Purpose Logic Input 4. An internal 10A current source pulls GPI4 to GND. Configure GPI4 to control watchdog timer functions or the programmable outputs. General-Purpose Logic Input 3. An internal 10A current source pulls GPI3 to GND. Configure GPI3 to control watchdog timer functions or the programmable outputs. General-Purpose Logic Input 2. An internal 10A current source pulls GPI2 to GND. Configure GPI2 to control watchdog timer functions or the programmable outputs. General-Purpose Logic Input 1. An internal 10A current source pulls GPI1 to GND. Configure GPI1 to control watchdog timer functions or the programmable outputs. Internal Power-Supply Voltage. Bypass VCC to GND with a 1F ceramic capacitor. VCC supplies power to the internal circuitry. VCC is internally powered from the highest of the monitored IN1-IN5 voltages. Do not use VCC to supply power to external circuitry. To externally supply VCC, see the Powering the MAX6889/MAX6890/MAX6891 section. Internal Digital Power-Supply Voltage. Bypass DBP to GND with a 1F ceramic capacitor. DBP supplies power to the EEPROM memory, the internal logic circuitry, and the programmable outputs. Do not use DBP to supply power to external circuitry. High-Voltage Input 8. Configure IN8 to detect voltage thresholds from 2.5V to 15.25V in 50mV increments, or 1.25V to 7.625V in 25mV increments. For improved noise immunity, bypass IN8 to GND with a 0.1F capacitor installed as close to the device as possible. Voltage Input 7. Configure IN7 to detect voltage thresholds between 1V and 5.5V in 20mV increments, or 0.5V to 3.05V in 10mV increments. For improved noise immunity, bypass IN7 to GND with a 0.1F capacitor installed as close to the device as possible.
MAX6889/MAX6890/MAX6891
12
10
7
MR
13 14 15
11 12 13
8 9 10
SDA SCL A0
16
14
--
A1
17
15
--
GPI4
18
16
11
GPI3
19
17
12
GPI2
20
18
13
GPI1
21
19
14
VCC
22
20
15
DBP
23
--
--
IN8
24
--
--
IN7
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9
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Pin Description (continued)
PIN MAX6889 MAX6890 MAX6891 NAME FUNCTION Voltage Input 6. Configure IN6 to detect voltage thresholds between 1V and 5.5V in 20mV increments, or 0.5V to 3.05V in 10mV increments. For improved noise immunity, bypass IN6 to GND with a 0.1F capacitor installed as close to the device as possible. Voltage Input 5. Configure IN5 to detect voltage thresholds between 1V and 5.5V in 20mV increments, or 0.5V to 3.05V in 10mV increments. For improved noise immunity, bypass IN5 to GND with a 0.1F capacitor installed as close to the device as possible. Voltage Input 4. Configure IN4 to detect voltage thresholds between 1V and 5.5V in 20mV increments, or 0.5V to 3.05V in 10mV increments. For improved noise immunity, bypass IN4 to GND with a 0.1F capacitor installed as close to the device as possible. Voltage Input 3. Configure IN3 to detect voltage thresholds between 1V and 5.5V in 20mV increments, or 0.5V to 3.05V in 10mV increments. For improved noise immunity, bypass IN3 to GND with a 0.1F capacitor installed as close to the device as possible. Voltage Input 2. Configure IN2 to detect voltage thresholds between 1V and 5.5V in 20mV increments, or 0.5V to 3.05V in 10mV increments. For improved noise immunity, bypass IN2 to GND with a 0.1F capacitor installed as close to the device as possible. High-Voltage Input 1. Configure IN1 to detect voltage thresholds from 2.5V to 13.2V in 50mV increments, or 1.25V to 7.625V in 25mV increments. For improved noise immunity, bypass IN1 to GND with a 0.1F capacitor installed as close to the device as possible. No Connection. Not internally connected. Programmable Output 1. Configurable, active-high, active-low, open-drain, or weak pullup output. PO1 pulls low with a 10A internal current sink for 1V < VCC < VUVLO. PO1 assumes its programmed conditional output state when VCC exceeds undervoltage lockout (UVLO) of 2.5V. Exposed Paddle. Internally connected to GND. Connect exposed paddle to GND or leave floating.
25
21
--
IN6
26
22
--
IN5
27
23
16
IN4
28
24
17
IN3
29
25
18
IN2
30
26
19
IN1
31
27
--
N.C.
32
28
20
PO1
EP
EP
EP
GND
10
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
Functional Diagram
GPI4 * GPI1 GPI2 GPI3 MARGIN MR
MAX6889/MAX6890/MAX6891
2.55V LDO OUTPUT IN1 IN_ DETECTOR OPEN-DRAIN OR WEAK PULLUP SWITCH 10k PO1 10A POWER-UP PULLDOWN PO_ OUTPUT
5.4V LDO LO/ HI VREF PROGRAMMABLE ARRAY TIMING BLOCK 1 TIMING BLOCK 2 TIMING BLOCK 3 TIMING BLOCK 4 TIMING BLOCK 5 TIMING BLOCK 6 TIMING BLOCK 7 TIMING BLOCK 8 TIMING BLOCK 9 TIMING BLOCK 10 MAIN OSCILLATOR VIRTUAL DIODES 2.55V LDO DBP 1F VCC 1F PO2 OUTPUT PO3 OUTPUT PO4 OUTPUT PO5 OUTPUT PO6 OUTPUT PO7 OUTPUT PO8 OUTPUT PO9 OUTPUT PO10 OUTPUT
IN2 IN3 IN4 IN5* IN6* IN7** IN8**
IN2 DETECTOR IN3 DETECTOR IN4 DETECTOR IN5 DETECTOR IN6 DETECTOR IN7 DETECTOR IN8 DETECTOR
PO2 PO3 PO4 PO5 PO6* PO7* PO8* PO9** PO10** EEPROM CHARGE PUMP CONFIG CONFIG REGISTERS EEPROM USER EEPROM
MAX6889 MAX6890 MAX6891
SDA 2-WIRE INTERFACE SCL A0 A1
GND
* FOR MAX6889/MAX6890 ONLY. ** FOR MAX6889 ONLY.
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
IN _ COMPARATORS LOGIC NETWORK FOR PO_ OUTPUT STAGES PO_
MR, GPI_, MARGIN
WATCHDOG TIMER
GPI_
SDA, SCL
SERIAL INTERFACE
REGISTER BANK EEPROM (USER AND CONFIG) BOOT CONTROLLER
ANALOG BLOCK DIGITAL BLOCK
Figure 1. Top-Level Block Diagram
Detailed Description
The MAX6889/MAX6890/MAX6891 EEPROM-configurable, multivoltage supply sequencers/supervisors monitor several voltage detector inputs and generalpurpose logic inputs, and feature programmable outputs for highly-configurable power-supply sequencing applications. The MAX6889 features eight voltage detector inputs and ten programmable outputs. The MAX6890 features six voltage detector inputs and eight programmable outputs, while the MAX6891 features four voltage detector inputs and five programmable outputs. Manual reset and margin disable inputs simplify board-level testing during the manufacturing process. All voltage detectors provide configurable thresholds for undervoltage detection. The high-voltage input (IN1) monitors voltages from 1.25V to 7.625V in 25mV increments, or 2.5V to 13.2V in 50mV increments. Inputs (IN2-IN7) monitor voltages from 0.5V to 3.05V in 10mV increments, or 1.0V to 5.5V in 20mV increments. An additional high-voltage input (IN8, MAX6889 only) monitors voltages from 1.25V to 7.625V in 25mV increments, or 2.5V to 15.25V in 50mV increments. To
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monitor thresholds from 0.1667V to 1.0167V in 3.3mV increments, the respective input voltage detector must be programmed for high impedance (high-Z) and an external voltage-divider must be connected. The host controller communicates with the MAX6889/MAX6890/MAX6891s' internal 512-bit user EEPROM, configuration EEPROM, and configuration registers through an SMBus/I2C-compatible serial interface (see Figure 1). Programmable output options include active-high, activelow, open drain, and weak pullup. Program each output to assert on any voltage detector input, general-purpose logic input, watchdog timer, or manual reset. Programmable timing delay blocks configure each output to wait between 25s and 1600ms before deasserting. The MAX6889/MAX6890/MAX6891 feature a watchdog timer for added flexibility. Program the watchdog timer to assert one or more programmable outputs. Program the watchdog timer to clear on a combination of one GPI_ input and one programmable output, one of the GPI_ inputs only, or one of the programmable outputs only. The initial and normal watchdog timeout periods are independently programmable from 6.25ms to 102.4s.
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891 MAX6889/MAX6890/MAX6891
Table 1. Programmable Features
FEATURE High-Voltage Input IN1 Positive Voltage Input IN2-IN7 (MAX6889) IN2-IN6 (MAX6890) IN2-IN4 (MAX6891) High-Voltage Input IN8 (MAX6889) Programmable Outputs PO1-PO10 (MAX6889) PO1-PO8 (MAX6890) PO1-PO5 (MAX6891) General-Purpose Logic Inputs: GPI1-GPI4 (MAX6889-MAX6890) GPI1-GPI3 (MAX6891) DESCRIPTION
* 2.5V to 13.2V threshold in 50mV increments. * 1.25V to 7.625V threshold in 25mV increments. * 1V to 5.5V threshold in 20mV increments. * 0.5V to 3.05V threshold in 10mV increments. * 0.1667V to 1.0167V threshold in 3.3mV increments in high-Z mode. * 2.5V to 15.25V threshold in 50mV increments. * 1.25V to 7.625V threshold in 25mV increments. * 0.1667V to 1.0167V threshold in 3.3mV increments in high-Z mode. * Active-high or active-low. * Open-drain or weak pullup output. * Dependent on MR, MARGIN, IN_, GPI_, and WD. * Programmable reset timeout periods of 25s, 1.5625ms, 6.25ms, 25ms, 50ms, 200ms, 400ms,
or 1.6s.
* Active-high or active-low logic levels. * Configure GPI_ as inputs to the watchdog timer or the programmable output stages. * Clear dependent on any combination of one GPI_ input and one programmable output, a GPI_
input only, or a programmable output only. Watchdog Timer
* Initial watchdog timeout period of 6.25ms, 25ms, 100ms, 400ms, 1.6s, 6.4s, 25.6s, or 102.4s. * Normal watchdog timeout period of 6.25ms, 25ms, 100ms, 400ms, 1.6s, 6.4s, 25.6s, or 102.4s. * Watchdog enable/disable.
Manual Reset Input (MR) VCC Power Mode Write Disable Configuration Lock
* Forces PO_ into the active output state when MR = GND. * PO_ deassert after MR releases high and the PO_ timeout period expires.
Programs whether the device is powered from the highest IN_ input or from an external supply connected to VCC. Locks user EEPROM based on PO_. Locks configuration registers and EEPROM.
Powering the MAX6889/MAX6890/MAX6891
The MAX6889/MAX6890/MAX6891 derive power from the voltage detector inputs: IN1-IN5 (MAX6889/ MAX6890), IN1-IN4 (MAX6891), or an external VCC supply. A virtual diode-ORing scheme selects the positive input that supplies power to the device (see the Functional Diagram). IN1 must be at least 4V, or one of IN2-IN5 (MAX6889/MAX6890)/IN2-IN4 (MAX6891) must be at least 2.7V to ensure device operation. An internal LDO regulates IN1 down to 5.4V. The highest input voltage on IN2-IN5 (MAX6889/ MAX6890)/IN2-IN4 (MAX6891) supplies power to the device, unless VIN1 > 6.5V, in which case IN1 supplies power to the device. For 4V < VIN1 < 6.5V and one of
VIN2-VIN5 > 2.7V, the input power source cannot be determined due to the dropout voltage of the LDO. Internal hysteresis ensures that the supply input that initially powered the device continues to power the device when multiple input voltages are within 50mV of each other. VCC powers the analog circuitry. Bypass VCC to GND with a 1F ceramic capacitor installed as close to the device as possible. The internal supply voltage, measured at VCC, equals the maximum of IN2-IN5 if VIN1 = 0V, or equals 5.4V when VIN1 > 6.5V. Do not use the internally generated VCC to provide power to external circuitry. Power cannot be supplied through highimpedance voltage detector inputs. To externally supply power through VCC:
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
1) Apply a voltage between 2.7V and 5.5V to one of VCC or IN2-IN5. 2) Program the internal/external VCC power EEPROM at AEh, Bit[2] = 1 (see Table 22). 3) Power down the device. Subsequent power-ups and software reboots require an externally supplied VCC to ensure the device is fully operational. The MAX6889/MAX6890/MAX6891 also generate a digital supply voltage (DBP) for the internal logic circuitry and the EEPROM. Bypass DBP to GND with a 1F ceramic capacitor installed as close to the device as possible. The nominal DBP output voltage is 2.55V. Do not use DBP to provide power to external circuitry. erwise the threshold exceeds the maximum operating voltage of IN1. IN2-IN7 The IN2-IN7 positive voltage detectors monitor voltages from 1V to 5.5V in 20mV increments, 0.5V to 3.05V in 10mV increments, or 0.1667V to 1.0167V in 3.3mV increments in high-Z mode. Use the following equations to set the threshold voltages for IN_:
V - 1V x = TH for 1V to 5.5V range 0.02V V - 0.5V x = TH for 0.5V to 3.05V range 0.1V V - 0.1667V x = TH for 0.1667V to 1.0167V high - Z range 0.0033V
Inputs
The MAX6889/MAX6890/MAX6891 contain multiple logic and voltage detector inputs. Each voltage detector input is monitored for undervoltage thresholds. Table 1 summarizes these various inputs. Set the threshold voltage for each voltage detector input with registers 00h-07h. Each threshold voltage is an undervoltage threshold. Set the threshold range for each voltage detector with register 08h. High-Voltage Input (IN1) IN1 offers threshold voltages of 2.5V to 13.2V in 50mV increments, or 1.25V to 7.625V in 25mV increments. Use the following equations to set the threshold voltages for IN1: V - 2.5V x = TH for 2.5V to 13.2V range 0.05V V - 1.25V x = TH for 1.25V to 7.625V range 0.025V where VTH is the desired threshold voltage and x is the decimal code for the desired threshold (Table 2). For the 2.5V to 13.2V range, x must equal 214 or less; othwhere VTH is the desired threshold voltage and x is the decimal code for the desired threshold (Table 3). For the 1V to 5.5V range, x must equal 225 or less; otherwise the threshold exceeds the maximum operating voltage of IN2-IN7. High-Voltage Input (IN8) Configure IN8 to detect positive thresholds from 2.5V to 15.25V in 50mV increments, 1.25V to 7.625V in 25mV increments, or 0.1667V to 1.0167V in 3.3mV increments in high-Z mode. Use the following equations to set the threshold voltages for IN8:
V - 2.5V x = TH for 2.5V to 15.25V range 0.05V V - 1.25V x = TH for 1.25V to 7.625V range 0.025V V - 0.1667V x = TH for 0.1667V to 1.0167V high - Z range 0.0033V
where VTH is the desired threshold voltage and x is the decimal code for the desired threshold (Table 4).
Table 2. IN1 Threshold Settings
REGISTER ADDRESS 00h 08h 09h EEPROM MEMORY ADDRESS 80h 88h 89h BIT RANGE [7:0] [0] [0] DESCRIPTION IN1 undervoltage detector threshold (V1) (see equations in the Inputs section) IN1 range selection. 0 = 2.5V to 13.2V range in 50mV increments. 1 = 1.25V to 7.625V range in 25mV increments. Must be set to "0" for normal operation
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891 MAX6889/MAX6890/MAX6891
Table 3. IN2-IN7 Threshold Settings
REGISTER ADDRESS 01h 02h 03h 04h 05h 06h EEPROM BIT MEMORY RANGE ADDRESS 81h 82h 83h 84h 85h 86h [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [1] [2] [3] 08h 88h [4] [5] [6] [7] [1] [2] [3] 09h 89h [4] [5] [6] IN5 input impedance. 0 = normal mode. 1 = high-Z mode, with a 0.1667V to 1.0167V range in 3.3mV increments. IN6 input impedance. 0 = normal mode. 1 = high-Z mode, with a 0.1667V to 1.0167V range in 3.3mV increments. IN7 input impedance. 0 = normal mode. 1 = high-Z mode, with a 0.1667V to 1.0167V range in 3.3mV increments. DESCRIPTION IN2 undervoltage detector threshold (V2) (see equations in the Inputs section) IN3 undervoltage detector threshold (V3) (see equations in the Inputs section) IN4 undervoltage detector threshold (V4) (see equations in the Inputs section) IN5 (MAX6889/MAX6890 only) undervoltage detector threshold (V5) (see equations in the Inputs section) IN6 (MAX6889/MAX6890 only) undervoltage detector threshold (V6) (see equations in the Inputs section) IN7 (MAX6889 only) undervoltage detector threshold (V7) (see equations in the Inputs section) IN2 range selection, 0 = 1V to 5.5V range in 20mV increments, 1 = 0.5V to 3.05V range in 10mV increments IN3 range selection, 0 = 1V to 5.5V range in 20mV increments, 1 = 0.5V to 3.05V range in 10mV increments IN4 range selection, 0 = 1V to 5.5V range in 20mV increments, 1 = 0.5V to 3.05V range in 10mV increments IN5 (MAX6889/MAX6890 only) range selection, 0 = 1V to 5.5V range in 20mV increments, 1 = 0.5V to 3.05V range in 10mV increments IN6 (MAX6889/MAX6890 only) range selection, 0 = 1V to 5.5V range in 20mV increments, 1 = 0.5V to 3.05V range in 10mV increments IN7 (MAX6889 only) range selection, 0 = 1V to 5.5V range in 20mV increments, 1 = 0.5V to 3.05V range in 10mV increments Not used IN2 input impedance. 0 = normal mode. 1 = high-Z mode, with a 0.1667V to 1.0167V range in 3.3mV increments. IN3 input impedance. 0 = normal mode. 1 = high-Z mode, with a 0.1667V to 1.0167V range in 3.3mV increments. IN4 input impedance. 0 = normal mode. 1 = high-Z mode, with a 0.1667V to 1.0167V range in 3.3mV increments.
GPI1-GPI4 The GPI1-GPI4 (General-Purpose Input) programmable logic inputs control power-supply sequencing (programmable outputs), reset/interrupt signaling, and watchdog functions (see the Configuring the Watchdog Timer section). Configure GPI1-GPI4 for active-low or active-high logic (Table 5). GPI1-GPI4 internally pull down to GND through a 10A current sink.
MR The manual reset (MR) input initiates a reset condition. See Table 6 to program the PO_ outputs to assert when MR is low. All affected programmable outputs remain asserted (see the Programmable Outputs section) for their PO_ timeout periods after MR releases high. An internal 10A current source pulls MR to DBP. Leave MR unconnected or connect to DBP if unused.
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Table 4. IN8 Threshold Settings
REGISTER ADDRESS 07h 08h EEPROM MEMORY ADDRESS 87h 88h BIT RANGE [7:0] [7] DESCRIPTION IN8 undervoltage detector threshold (V8) (see equations in the Inputs section) IN8 range selection. 0 = 2.5V to 15.25V range in 50mV increments. 1 = 1.25V to 7.625V range in 25mV increments. IN8 input impedance. 0 = normal mode. 1 = high-Z mode, with a 0.1667V to 1.0167V range in 3.3mV increments.
09h
89h
[7]
Table 5. GPI1-GPI4 Active Logic States
REGISTER ADDRESS EEPROM ADDRESS BIT RANGE [0] 28h A8h [1] [2] [3] GPI1. 0 = active-low, 1 = active-high. GPI2. 0 = active-low, 1 = active-high. GPI3. 0 = active-low, 1 = active-high. GPI4 (MAX6889/MAX6890 only). 0 = active-low, 1 = active-high. DESCRIPTION
MARGIN MARGIN allows system-level testing while power supplies exceed the normal ranges. Driving MARGIN low forces the programmable outputs to hold the last state while system-level testing occurs. Leave MARGIN unconnected or connect to DBP if unused. An internal 10A current source pulls MARGIN to DBP. The state of each programmable output does not change while MARGIN = GND. MARGIN overrides MR if both assert at the same time.
configured as active-high is considered asserted when that output is logic-high. The voltage monitors generate fault signals (logical 0) to the MAX6889/MAX6890/MAX6891s' logic array when an input voltage is below the programmed undervoltage threshold. For example, the PO3 (Table 9) programmable output may depend on the IN1 undervoltage threshold, and the state of GPI1. Write "1"s to R10h[0] and R11h[1] to configure as indicated. IN1 must be above the undervoltage threshold (Table 2) and GPI1 must be inactive (Table 5) to be a logic "1," then PO3 deasserts. The logic state of PO3, in this example, is equivalent to the logical statement: "V1 * GPI1." Registers 0Ah through 27h configure each of the programmable outputs. Programmable timing blocks set the PO_ timeout period from 25s to 1600ms for each programmable output. See Table 17 to set the active state (active-high or active-low) for each programmable output and Tables 18 and 19 to select the output stage types, and PO_ timeout periods for each output. Each programmable output allows a different set of conditions to assert each output as shown in Tables 7-16.
Programmable Outputs
The MAX6889 features ten programmable outputs, the MAX6890 features eight programmable outputs, and the MAX6891 features five programmable outputs. Selectable output stage configurations include: activelow or active-high, open drain, or weak pullup. During power-up, the programmable outputs pull to GND with an internal 10A current sink for 1V < VCC < VUVLO. The programmable outputs remain in their active states until their respective PO timeout period expires, and all of the programmed conditions are met for each output. Any output programmed to depend on no condition always remains in its active state (Table 17). An output
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
Table 6. Programmable Output Behavior and MR
REGISTER ADDRESS 0Bh 0Eh 11h 14h 17h 1Ah 1Dh 20h 23h 26h EEPROM MEMORY ADDRESS 8Bh 8Eh 91h 94h 97h 9Ah 9Dh A0h A3h A6h BIT RANGE [5] [5] [5] [5] [5] [5] [5] [5] [5] [5] DESCRIPTION PO1. 0 = PO1 independent of MR, 1 = PO1 asserts when MR = low. PO2. 0 = PO2 independent of MR, 1 = PO2 asserts when MR = low. PO3. 0 = PO3 independent of MR, 1 = PO3 asserts when MR = low. PO4. 0 = PO4/PO2 independent of MR, 1 = PO4 asserts when MR = low. PO5. 0 = PO5 independent of MR, 1 = PO5 asserts when MR = low. PO6 (MAX6889/MAX6890 only). 0 = PO6 independent of MR, 1 = PO6 asserts when MR = low. PO7 (MAX6889/MAX6890 only). 0 = PO7 independent of MR, 1 = PO7 asserts when MR = low. PO8 (MAX6889/MAX6890 only). 0 = PO8 independent of MR, 1 = PO8 asserts when MR = low. PO9 (MAX6889 only). 0 = PO9 independent of MR, 1 = PO9 asserts when MR = low. PO10 (MAX6889 only). 0 = PO10 independent of MR, 1 = PO10 asserts when MR = low.
MAX6889/MAX6890/MAX6891 MAX6889/MAX6890/MAX6891
Table 7. PO1 Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] [3] 0Ah 8Ah [4] [5] [6] [7] [0] [1] [2] 0Bh 8Bh [3] [4] [5] [7:6] OUTPUT ASSERTION CONDITIONS 1 = PO1 assertion depends on IN1 undervoltage threshold (Table 2) 1 = PO1 assertion depends on IN2 undervoltage threshold (Table 3) 1 = PO1 assertion depends on IN3 undervoltage threshold (Table 3) 1 = PO1 assertion depends on IN4 undervoltage threshold (Table 3) 1 = PO1 assertion depends on IN5 (MAX6889/MAX6890 only) undervoltage threshold (Table 3) 1 = PO1 assertion depends on IN6 (MAX6889/MAX6890 only) undervoltage threshold (Table 3) 1 = PO1 assertion depends on IN7 (MAX6890 only) undervoltage threshold (Table 3) 1 = PO1 assertion depends on IN8 (MAX6890 only) undervoltage threshold (Table 4) 1 = PO1 assertion depends on watchdog (Table 20) 1 = PO1 assertion depends on GPI1 (Table 5) 1 = PO1 assertion depends on GPI2 (Table 5) 1 = PO1 assertion depends on GPI3 (Table 5) 1 = PO1 assertion depends on GPI4 (MAX6889/MAX6890 only) (Table 5) 1 = PO1 asserts when MR = low (Table 6) Not used
Note: Table 7 only applies to PO1. Write a "0" to a bit to make the PO1 output independent of the respective signal (IN_ thresholds, WD, GPI_, or MR).
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Table 8. PO2 Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] [3] 0Dh 8Dh [4] [5] [6] [7] [0] [1] [2] 0Eh 8Eh [3] [4] [5] [7:6] OUTPUT ASSERTION CONDITIONS 1 = PO2 assertion depends on IN1 undervoltage threshold (Table 2) 1 = PO2 assertion depends on IN2 undervoltage threshold (Table 3) 1 = PO2 assertion depends on IN3 undervoltage threshold (Table 3) 1 = PO2 assertion depends on IN4 undervoltage threshold (Table 3) 1 = PO2 assertion depends on IN5 (MAX6889/MAX6890 only) undervoltage threshold (Table 3) 1 = PO2 assertion depends on IN6 (MAX6889/MAX6890 only) undervoltage threshold (Table 3) 1 = PO2 assertion depends on IN7 (MAX6890 only) undervoltage threshold (Table 3) 1 = PO2 assertion depends on IN8 (MAX6890 only) undervoltage threshold (Table 4) 1 = PO2 assertion depends on watchdog (Table 20) 1 = PO2 assertion depends on GPI1 (Table 5) 1 = PO2 assertion depends on GPI2 (Table 5) 1 = PO2 assertion depends on GPI3 (Table 5) 1 = PO2 assertion depends on GPI4 (MAX6889/MAX6890 only) (Table 5) 1 = PO2 asserts when MR = low (Table 6) Not used
Note: Table 8 only applies to PO2. Write a "0" to a bit to make the PO2 output independent of the respective signal (IN_ thresholds, WD, GPI_, or MR).
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Table 9. PO3 Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] [3] 10h 90h [4] [5] [6] [7] [0] [1] [2] 11h 11h [3] [4] [5] [7:6] OUTPUT ASSERTION CONDITIONS 1 = PO3 assertion depends on IN1 undervoltage threshold (Table 2) 1 = PO3 assertion depends on IN2 undervoltage threshold (Table 3) 1 = PO3 assertion depends on IN3 undervoltage threshold (Table 3) 1 = PO3 assertion depends on IN4 undervoltage threshold (Table 3) 1 = PO3 assertion depends on IN5 (MAX6889/MAX6890 only) undervoltage threshold (Table 3) 1 = PO3 assertion depends on IN6 (MAX6889/MAX6890 only) undervoltage threshold (Table 3) 1 = PO3 assertion depends on IN7 (MAX6890 only) undervoltage threshold (Table 3) 1 = PO3 assertion depends on IN8 (MAX6890 only) undervoltage threshold (Table 4) 1 = PO3 assertion depends on watchdog (Table 20) 1 = PO3 assertion depends on GPI1 (Table 5) 1 = PO3 assertion depends on GPI2 (Table 5) 1 = PO3 assertion depends on GPI3 (Table 5) 1 = PO3 assertion depends on GPI4 (MAX6889/MAX6890 only) (Table 5) 1 = PO3 asserts when MR = low (Table 6) Not used
Note: Table 9 only applies to PO3. Write a "0" to a bit to make the PO3 output independent of the respective signal (IN_ thresholds, WD, GPI_, or MR).
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Table 10. PO4 Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] [3] 13h 93h [4] [5] [6] [7] [0] [1] [2] 14h 14h [3] [4] [5] [7:6] OUTPUT ASSERTION CONDITIONS 1 = PO4 assertion depends on IN1 undervoltage threshold (Table 2) 1 = PO4 assertion depends on IN2 undervoltage threshold (Table 3) 1 = PO4 assertion depends on IN3 undervoltage threshold (Table 3) 1 = PO4 assertion depends on IN4 undervoltage threshold (Table 3) 1 = PO4 assertion depends on IN5 (MAX6889/MAX6890 only) undervoltage threshold (Table 3) 1 = PO4 assertion depends on IN6 (MAX6889/MAX6890 only) undervoltage threshold (Table 3) 1 = PO4 assertion depends on IN7 (MAX6890 only) undervoltage threshold (Table 3) 1 = PO4 assertion depends on IN8 (MAX6890 only) undervoltage threshold (Table 4) 1 = PO4 assertion depends on watchdog (Table 20) 1 = PO4 assertion depends on GPI1 (Table 5) 1 = PO4 assertion depends on GPI2 (Table 5) 1 = PO4 assertion depends on GPI3 (Table 5) 1 = PO4 assertion depends on GPI4 (MAX6889/MAX6890 only) (Table 5) 1 = PO4 asserts when MR = low (Table 6) Not used
Note: Table 10 only applies to PO4. Write a "0" to a bit to make the PO4 output independent of the respective signal (IN_ thresholds, WD, GPI_, or MR).
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Table 11. PO5 Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] [3] 16h 96h [4] [5] [6] [7] [0] [1] [2] 17h 17h [3] [4] [5] [7:6] OUTPUT ASSERTION CONDITIONS 1 = PO5 assertion depends on IN1 undervoltage threshold (Table 2) 1 = PO5 assertion depends on IN2 undervoltage threshold (Table 3) 1 = PO5 assertion depends on IN3 undervoltage threshold (Table 3) 1 = PO5 assertion depends on IN4 undervoltage threshold (Table 3) 1 = PO5 assertion depends on IN5 (MAX6889/MAX6890 only) undervoltage threshold (Table 3) 1 = PO5 assertion depends on IN6 (MAX6889/MAX6890 only) undervoltage threshold (Table 3) 1 = PO5 assertion depends on IN7 (MAX6890 only) undervoltage threshold (Table 3) 1 = PO5 assertion depends on IN8 (MAX6890 only) undervoltage threshold (Table 4) 1 = PO5 assertion depends on watchdog (Table 20) 1 = PO5 assertion depends on GPI1 (Table 5) 1 = PO5 assertion depends on GPI2 (Table 5) 1 = PO5 assertion depends on GPI3 (Table 5) 1 = PO5 assertion depends on GPI4 (MAX6889/MAX6890 only) (Table 5) 1 = PO5 asserts when MR = low (Table 6) Not used
Note: Table 11 only applies to PO5. Write a "0" to a bit to make the PO5 output independent of the respective signal (IN_ thresholds, WD, GPI_, or MR).
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Table 12. PO6 (MAX6889/MAX6890 Only) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] 19h 99h [3] [4] [5] [6] [7] [0] [1] [2] 1Ah 9Ah [3] [4] [5] [7:6] OUTPUT ASSERTION CONDITIONS 1 = PO6 assertion depends on IN1 undervoltage threshold (Table 2) 1 = PO6 assertion depends on IN2 undervoltage threshold (Table 3) 1 = PO6 assertion depends on IN3 undervoltage threshold (Table 3) 1 = PO6 assertion depends on IN4 undervoltage threshold (Table 3) 1 = PO6 assertion depends on IN5 undervoltage threshold (Table 3) 1 = PO6 assertion depends on IN6 undervoltage threshold (Table 3) 1 = PO6 assertion depends on IN7 (MAX6890 only) undervoltage threshold (Table 3) 1 = PO6 assertion depends on IN8 (MAX6890 only) undervoltage threshold (Table 4) 1 = PO6 assertion depends on watchdog (Table 20) 1 = PO6 assertion depends on GPI1 (Table 5) 1 = PO6 assertion depends on GPI2 (Table 5) 1 = PO6 assertion depends on GPI3 (Table 5) 1 = PO6 assertion depends on GPI4 (Table 5) 1 = PO4 asserts when MR = low (Table 6) Not used
Note: Table 12 only applies to PO6 (MAX6889/MAX6890 only). Write a "0" to a bit to make the PO6 output independent of the respective signal (IN_ thresholds, WD, GPI_, or MR).
Table 13. PO7 (MAX6889/MAX6890 Only) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] 1Ch 9Ch [3] [4] [5] [6] [7] [0] [1] [2] 1Dh 9Dh [3] [4] [5] [7:6] OUTPUT ASSERTION CONDITIONS 1 = PO7 assertion depends on IN1 undervoltage threshold (Table 2) 1 = PO7 assertion depends on IN2 undervoltage threshold (Table 3) 1 = PO7 assertion depends on IN3 undervoltage threshold (Table 3) 1 = PO7 assertion depends on IN4 undervoltage threshold (Table 3) 1 = PO7 assertion depends on IN5 undervoltage threshold (Table 3) 1 = PO7 assertion depends on IN6 undervoltage threshold (Table 3) 1 = PO7 assertion depends on IN7 (MAX6890 only) undervoltage threshold (Table 3) 1 = PO7 assertion depends on IN8 (MAX6890 only) undervoltage threshold (Table 4) 1 = PO7 assertion depends on watchdog (Table 20) 1 = PO7 assertion depends on GPI1 (Table 5) 1 = PO7 assertion depends on GPI2 (Table 5) 1 = PO7 assertion depends on GPI3 (Table 5) 1 = PO7 assertion depends on GPI4 (Table 5) 1 = PO7 asserts when MR = low (Table 6) Not used
Note: Table 13 only applies to PO7 (MAX6889/MAX6890 only). Write a "0" to a bit to make the PO7 output independent of the respective signal (IN_ thresholds, WD, GPI_, or MR). 22 ______________________________________________________________________________________
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Table 14. PO8 (MAX6889/MAX6890 Only) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] 1Fh 9Fh [3] [4] [5] [6] [7] [0] [1] [2] 20h A0h [3] [4] [5] [7:6] OUTPUT ASSERTION CONDITIONS 1 = PO8 assertion depends on IN1 undervoltage threshold (Table 2) 1 = PO8 assertion depends on IN2 undervoltage threshold (Table 3) 1 = PO8 assertion depends on IN3 undervoltage threshold (Table 3) 1 = PO8 assertion depends on IN4 undervoltage threshold (Table 3) 1 = PO8 assertion depends on IN5 undervoltage threshold (Table 3) 1 = PO8 assertion depends on IN6 undervoltage threshold (Table 3) 1 = PO8 assertion depends on IN7 (MAX6890 only) undervoltage threshold (Table 3) 1 = PO8 assertion depends on IN8 (MAX6890 only) undervoltage threshold (Table 4) 1 = PO8 assertion depends on watchdog (Table 20) 1 = PO8 assertion depends on GPI1 (Table 5) 1 = PO8 assertion depends on GPI2 (Table 5) 1 = PO8 assertion depends on GPI3 (Table 5) 1 = PO8 assertion depends on GPI4 (Table 5) 1 = PO8 asserts when MR = low (Table 6) Not used
MAX6889/MAX6890/MAX6891
Note: Table 14 only applies to PO8 (MAX6889/MAX6890 only). Write a "0" to a bit to make the PO8 output independent of the respective signal (IN_ thresholds, WD, GPI_, or MR).
Table 15. PO9 (MAX6889 Only) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] 22h A2h [3] [4] [5] [6] [7] [0] [1] [2] 23h A3h [3] [4] [5] [7:6] OUTPUT ASSERTION CONDITIONS 1 = PO9 assertion depends on IN1 undervoltage threshold (Table 2) 1 = PO9 assertion depends on IN2 undervoltage threshold (Table 3) 1 = PO9 assertion depends on IN3 undervoltage threshold (Table 3) 1 = PO9 assertion depends on IN4 undervoltage threshold (Table 3) 1 = PO9 assertion depends on IN5 undervoltage threshold (Table 3) 1 = PO9 assertion depends on IN6 undervoltage threshold (Table 3) 1 = PO9 assertion depends on IN7 undervoltage threshold (Table 3) 1 = PO9 assertion depends on IN8 undervoltage threshold (Table 4) 1 = PO9 assertion depends on watchdog (Table 20) 1 = PO9 assertion depends on GPI1 (Table 5) 1 = PO9 assertion depends on GPI2 (Table 5) 1 = PO9 assertion depends on GPI3 (Table 5) 1 = PO9 assertion depends on GPI4 (Table 5) 1 = PO9 asserts when MR = low (Table 6) Not used
Note: Table 15 only applies to PO9 (MAX6889 only). Write a "0" to a bit to make the PO9 output independent of the respective signal (IN_ thresholds, WD, GPI_, or MR). ______________________________________________________________________________________ 23
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Table 16. PO10 (MAX6889 Only) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] 25h A5h [3] [4] [5] [6] [7] [0] [1] [2] 26h A6h [3] [4] [5] [7:6] OUTPUT ASSERTION CONDITIONS 1 = PO10 assertion depends on IN1 undervoltage threshold (Table 2) 1 = PO10 assertion depends on IN2 undervoltage threshold (Table 3) 1 = PO10 assertion depends on IN3 undervoltage threshold (Table 3) 1 = PO10 assertion depends on IN4 undervoltage threshold (Table 3) 1 = PO10 assertion depends on IN5 undervoltage threshold (Table 3) 1 = PO10 assertion depends on IN6 undervoltage threshold (Table 3) 1 = PO10 assertion depends on IN7 undervoltage threshold (Table 3) 1 = PO10 assertion depends on IN8 undervoltage threshold (Table 4) 1 = PO10 assertion depends on watchdog (Table 20) 1 = PO10 assertion depends on GPI1 (Table 5) 1 = PO10 assertion depends on GPI2 (Table 5) 1 = PO10 assertion depends on GPI3 (Table 5) 1 = PO10 assertion depends on GPI4 (Table 5) 1 = PO10 asserts when MR = low (Table 6) Not used
Note: Table 16 only applies to PO10 (MAX6890 only). Write a "0" to a bit to make the PO10 output independent of the respective signal (IN_ thresholds, WD, GPI_, or MR).
Table 17. Programmable Output Active States
REGISTER ADDRESS 0Ch 0Fh 12h 15h 18h 1Bh 1Eh 21h 24h 27h EEPROM MEMORY ADDRESS 8Ch 8Fh 92h 95h 98h 9Bh 9Eh A1h A4h A7h BIT RANGE [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] AFFECTED OUTPUT PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 0 = active-low, 1 = active-high 0 = active-low, 1 = active-high 0 = active-low, 1 = active-high 0 = active-low, 1 = active-high 0 = active-low, 1 = active-high MAX6889/MAX6890 only. 0 = active-low, 1 = active-high. MAX6889/MAX6890 only. 0 = active-low, 1 = active-high. MAX6889/MAX6890 only. 0 = active-low, 1 = active-high. MAX6889 only. 0 = active-low, 1 = active-high. MAX6889 only. 0 = active-low, 1 = active-high. DESCRIPTION
24
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Output Stage Configurations Independently configure each programmable output as active-high or active-low (Table 17). Additionally, configure each programmable output as open drain or weak pullup (Table 18). Finally, set the PO_ timeout period for each programmable output (Table 19). The programmable outputs can sink up to 4mA. Weak Pullup Output Configuration The MAX6889/MAX6890/MAX6891s' programmable outputs have a pullup resistance (10k, typ) connected to the internal 2.55V LDO output to provide weak pullup outputs. Open-Drain Output Configuration Connect an external pullup resistor from the programmable output to an external voltage when configured as an open-drain output. Open-drain configured outputs may be pulled up to 13.2V. Choose the pullup resistor depending on the number of devices connected to the open-drain output and the allowable current consumption. The open-drain output configuration allows wireORed connections, and provides flexibility in setting the pullup current. Configuring the Watchdog Timer (Registers 29h-2Ah) A watchdog timer monitors microprocessor software execution for a stalled condition and resets the microprocessor if it stalls. The output of the watchdog timer (one of the programmable outputs) connects to the reset input or a nonmaskable interrupt of the microprocessor. Registers 29h-2Ah configure the watchdog functionality of the MAX6889/MAX6890/MAX6891. Program the watchdog timer to assert one or more programmable outputs (see Tables 7-16). Program the watchdog timer to reset on one of the GPI_ inputs, one of the programmable outputs, or a combination of one GPI_ input and one programmable output. The watchdog timer features independent initial and normal watchdog timeout periods. The initial watchdog timeout period applies immediately after power-up, after a software reboot, after a reset event takes place, or after enabling the watchdog timer. The initial watchdog timeout period allows the microprocessor to perform its initialization process. If no pulse occurs during the initial watchdog timeout period, the microprocessor is taking too long to initialize, indicating a potential problem. The normal watchdog timeout period applies after the initial watchdog timeout period occurs. The normal watchdog timeout period monitors a pulsed output of the microprocessor that indicates when normal processor behavior occurs. If no pulse occurs during the normal watchdog timeout period, this indicates that the processor has stopped operating or is stuck in an infinite execution loop. Register 2Ah programs the initial and normal watchdog timeout periods, and enables or disables the watchdog timer. See Tables 20 and 21 for a summary of the watchdog behavior. Configuration Lock Lock the configuration register bank and configuration EEPROM contents after initial programming by setting the lock bit high (see Table 22). Locking the configuration prevents write operations to all registers except the configuration lock register. Clear the lock bit to reconfigure the device. Internal/External VCC Power The MAX6889/MAX6890/MAX6891 can generate an internal VCC, or VCC can be externally supplied (see Table 22). To internally generate VCC from the highest voltage on IN1-IN5 set register 2Eh and EEPROM address AEh Bit[2] = 0. To use an externally supplied, always-on V CC ensure register 2Eh and EEPROM address AEh Bit[2] =1 (see the Powering the MAX6889/ MAX6890/MAX6891 section). Write Disable A unique write-disable feature protects the MAX6889/ MAX6890/MAX6891 from inadvertent user-EEPROM writes. As input voltages that power the serial interface, a microprocessor, or any other writing-devices fall, unintentional data may be written onto the data bus. The user-EEPROM write-disable function (see Table 23) ensures that unintentional data does not corrupt the MAX6889/MAX6890/MAX6891 EEPROM data.
MAX6889/MAX6890/MAX6891
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Table 18. Programmable Output Stage Options
REGISTER ADDRESS 0Ch 0Fh 12h 15h 18h 1Bh 1Eh 21h 24h 27h EEPROM MEMORY ADDRESS 8Ch 8Fh 92h 95h 98h 9Bh 9Eh A1h A4h A7h BIT RANGE [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] AFFECTED OUTPUT PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 DESCRIPTION 0 = weak pullup, 1 = open drain 0 = weak pullup, 1 = open drain 0 = weak pullup, 1 = open drain 0 = weak pullup, 1 = open drain 0 = weak pullup, 1 = open drain MAX6889/MAX6890 only. 0 = weak pullup, 1 = open drain. MAX6889/MAX6890 only. 0 = weak pullup, 1 = open drain. MAX6889/MAX6890 only. 0 = weak pullup, 1 = open drain. MAX6889 only. 0 = weak pullup, 1 = open drain. MAX6889 only. 0 = weak pullup, 1 = open drain.
Table 19. PO_ Timeout Periods
REGISTER ADDRESS 0Ch 0Fh 12h 15h 18h 1Bh 1Eh 21h 24h 27h EEPROM MEMORY ADDRESS 8Ch 8Fh 92h 95h 98h 9Bh 9Eh A1h A4h A7h BIT RANGE [4:2] [4:2] [4:2] [4:2] [4:2] [4:2] [4:2] [4:2] [4:2] [4:2] PO1 PO2 PO3 PO4 PO5 PO6 (MAX6889/MAX6890) PO7 (MAX6889/MAX6890) PO8 (MAX6889/MAX6890) PO9 (MAX6889 only) PO10 (MAX6889 only) 000 = 25s 001 = 1.5625ms 010 = 6.25ms 011 = 25ms 100 = 50ms 101 = 200ms 110 = 400ms 111 = 1600ms AFFECTED OUTPUTS DESCRIPTION
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Table 20. Watchdog Inputs
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION
[1:0]
Watchdog Input Selection: 00 = GPI1 input 01 = GPI2 input 10 = GPI3 input 11 = GPI4 input (MAX6889/MAX6890 only). Selects GPI3 on MAX6891. Watchdog Internal Input Selection: 0000 = PO1 0001 = PO2 0010 = PO3 0011 = PO4 0100 = PO5 0101 = PO6 (MAX6889/MAX6890 only) 0110 = PO7 (MAX6889/MAX6890 only) 0111 = PO8 (MAX6889/MAX6890 only) 1000 = PO9 (MAX6889 only) 1001 = PO10 (MAX6889 only) [1011] to [1111] = WD is not affected by PO_ Watchdog Dependency on Inputs: 00 = Watchdog not dependent on any input 01 = Watchdog clear depends on selected GPI_ input only 01 = Watchdog clear depends on selected PO_ input only 11 = Watchdog clear depends on both selected GPI_ and PO_ inputs
29h
A9h
[5:2]
[7:6]
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Table 21. Watchdog Timeout Period Selection
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE Normal Watchdog Timeout Period: 000 = 6.25ms 001 = 25ms 010 = 100ms 011 = 400ms 100 = 1.6s 101 = 6.4s 110 = 25.6s 111 = 102.4s Initial Watchdog Timeout Period (immediately following power-up, reset event, or enabling watchdog): 000 = 6.25ms 001 = 25ms 010 = 100ms 011 = 400ms 100 = 1.6s 101 = 6.4s 110 = 25.6s 111 = 102.4s Watchdog Enable 0 = Disables watchdog timer 1 = Enables watchdog timer Not used DESCRIPTION
[2:0]
2Ah
AAh [5:3]
[6] [7]
Table 22. Configuration Lock and Internal/External VCC Power Register
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] [1] 2Eh AEh [2] [7:3] 0 = Configuration unlocked 1 = Configuration locked Not used Internal/External VCC Power: 0 = VCC internally generated 1 = VCC externally supplied Not used DESCRIPTION
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Table 23. Write Disable Register
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] [1] [2] [3] 2Ch ACh [4] [5] [6] [7] [0] 2Dh ADh [1] [7:2] 0 = Write is not disabled if PO5 asserts 1 = Write disabled if PO5 asserts 0 = Write is not disabled if PO6 asserts 1 = Write disabled if PO6 asserts 0 = Write is not disabled if PO7 asserts 1 = Write disabled if PO7 asserts 0 = Write is not disabled if PO8 asserts 1 = Write disabled if PO8 asserts 0 = Write is not disabled if PO9 asserts 1 = Write disabled if PO9 asserts 0 = Write is not disabled if PO10 asserts 1 = Write disabled if PO10 asserts Not used DESCRIPTION 0 = Write is not disabled if PO1 asserts 1 = Write disabled if PO1 asserts 0 = Write is not disabled if PO2 asserts 1 = Write disabled if PO2 asserts 0 = Write is not disabled if PO3 asserts 1 = Write disabled if PO3 asserts 0 = Write is not disabled if PO4 asserts 1 = Write disabled if PO4 asserts
Configuring the MAX6889/MAX6890/MAX6891
The MAX6889/MAX6890/MAX6891 factory-default configuration sets all registers to 0h, except bits in Tables 17 and 18, which are set to 1h. Factory-default configuration sets all PO_'s as active-high, open drain (all outputs are high impedance until the device is configured by the user). Each device requires configuration before full power is applied to the system. To configure the MAX6889/MAX6890/MAX6891, first apply an input voltage to IN1, or one of IN2-IN5 or VCC (see the Powering the MAX6889/MAX6890/MAX6891 section). VIN1 > 4V, or one of VIN2-VIN5 or VCC > 2.7V to ensure device operation. Next, transmit data through the serial interface. Use the block write protocol to quickly configure the device. Write to the configuration registers first to ensure the device is configured properly. After completing the setup procedure, use the read word or block read protocol to read back the data from the configuration registers. Lastly, use the write byte or block
write protocol to write this data to the EEPROM registers. After completing the EEPROM register configuration, apply full power to the system to begin normal operation. The nonvolatile EEPROM stores the latest configuration upon removal of power. Write 0s to all EEPROM registers to clear the memory. Software Reboot A software reboot allows the user to restore the EEPROM configuration to the volatile registers without cycling the power supplies. Use the send byte command with data byte C4h to initiate a software reboot. The 3ms (max) power-up delay also applies after a software reboot.
Configuration EEPROM
The configuration EEPROM addresses range from 80h to AEh. Write data to the configuration EEPROM to automatically set up the MAX6889/MAX6890/MAX6891 upon power-up. Data is transferred from the configuration EEPROM to the configuration registers when V CC exceeds UVLO during power-up or after a software
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reboot. After V CC exceeds UVLO, an internal 1MHz clock starts after a 5s delay, and data transfer begins. Data transfer disables access to the configuration registers and EEPROM. The data transfer from EEPROM to configuration registers takes 3ms (max). Read configuration EEPROM data at any time after power-up or software reboot. Write commands to the configuration EEPROM are allowed at any time after power-up or software reboot, unless the configuration lock bit is set (see Table 22). The maximum cycle time to write a single byte is 11ms (max).
User EEPROM
The 512-bit, user-EEPROM addresses range from 40h to 7Fh (see Figure 2). Store software revision data, board revision data, and other data in these registers. The maximum cycle time to write a single byte is 11ms (max). Configuration Register Bank and EEPROM The configuration registers can be directly modified through the serial interface without modifying the EEPROM, after the power-up procedure terminates and the configuration EEPROM data has been loaded into the configuration register bank. Use the write byte or block write protocols to write directly to the configuration registers. Changes to the configuration registers take effect immediately and are lost upon power removal. At device power-up, the register bank loads configuration data from the EEPROM. Configuration data may be directly altered in the register bank during application development, allowing maximum flexibility. Transfer the new configuration data byte-by-byte to the configuration EEPROM with the write byte protocol. The next device power-up or software reboot automatically loads the new configuration. SMBus/I2C-Compatible Serial Interface The MAX6889/MAX6890/MAX6891 feature an I2C/SMBuscompatible 2-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX6889/MAX6890/MAX6891 and the master device at clock rates up to 400kHz. Figure 3 shows the 2-wire interface timing diagram. The MAX6889/MAX6890/MAX6891 are transmit/receive slave-only devices, relying upon a
00h
REGISTER BANK
37h RESERVED 40h USER EEPROM 7Fh 80h
CONFIGURATION EEPROM
AEh
Figure 2. Memory Map
SDA tBUF tSU:STA tLOW SCL tHIGH tHD:STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD:DAT tHD:STA tSU:STO
tSU:DAT
Figure 3. Serial-Interface Timing Details 30 ______________________________________________________________________________________
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master device to generate a clock signal. The master device (typically a microcontroller) generates SCL and initiates data transfer on the bus. A master device communicates to the MAX6889/ MAX6890/MAX6891 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (SR) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. SCL is a logic input, while SDA is an open-drain input/output. SCL and SDA both require external pullup resistors to generate the logic-high voltage. Use 4.7k resistors for most applications. Bit Transfer Each clock pulse transfers one data bit. The data on SDA must remain stable while SCL is high (Figure 4), otherwise the MAX6889/MAX6890/MAX6891 register a START or STOP condition (Figure 5) from the master. SDA and SCL idle high when the bus is not busy. Start and Stop Conditions A master device signals the beginning of a transmission with a START (S) condition (Figure 5) by transitioning SDA from high to low while SCL is high. The master device issues a STOP (P) condition (Figure 5) by transitioning SDA from low to high while SCL is high. A STOP condition frees the bus for another transmission. The bus remains active if a REPEATED START condition is generated, such as in the read byte or block read protocol (see Figure 8). Both SCL and SDA are high when the bus is not busy. Early STOP Conditions The MAX6889/MAX6890/MAX6891 recognize a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition. This condition is not a legal I2C format. At least one clock pulse must separate any START and STOP condition. Repeated START Conditions A REPEATED START (SR) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation (see Figure 8). SR may also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX6889/MAX6890/MAX6891 serial interface supports continuous write operations with or without an SR condition separating them. Continuous read operations require SR conditions because of the change in direction of data flow. Acknowledge The acknowledge bit (ACK) is the 9th bit attached to any 8-bit data word. The receiving device always generates an ACK. The MAX6889/MAX6890/MAX6891 generate an ACK when receiving an address or data by pulling SDA low during the 9th clock period (Figure 6). When transmitting data, such as when the master device reads data back from the MAX6889/MAX6890/MAX6891, the MAX6889/MAX6890/MAX6891 wait for the master device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. In the event of an unsuccessful
MAX6889/MAX6890/MAX6891 MAX6889/MAX6890/MAX6891 MAX6889/MAX6890/MAX6891 MAX6889/MAX6890/MAX6891
SDA
SDA
SCL SCL S P
DATA LINE STABLE, CHANGE OF DATA ALLOWED DATA VALID
START CONDITION
STOP CONDITION
Figure 4. Bit Transfer
Figure 5. Start and Stop Conditions 31
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data transfer, the bus master should reattempt communication at a later time. The MAX6889/MAX6890/ MAX6891 generate a NACK after the command byte during a software reboot, while writing to the EEPROM, or when receiving an illegal memory address. Slave Address SA7 through SA4 represent the standard 2-wire interface address (1010) for devices with EEPROM. SA3 and SA2 correspond to the A1 and A0 address inputs of the MAX6889/MAX6890/MAX6891 (hardwired as logic-low or logic-high). SA0 is a read/write flag bit (0 = write, 1 = read). The A0 and A1 address inputs allow up to four MAX6889/MAX6890 to connect to one bus, while the A0 address input allows up to two MAX6891s to connect to one bus. Connect A0 and A1 to GND or to the 2-wire serial-interface power supply (see Figure 7). The MAX6889/MAX6890 slave address conforms to the following table:
SA7 (MSB) SA6 SA5 SA4 SA3 SA2 SA1 SA0 (LSB) 1 0 1 0 A1 A0 X R/W
X = Don't Care
The MAX6891 slave address conforms to the following table:
SA7 (MSB) SA6 SA5 SA4 SA3 SA2 SA1 SA0 (LSB) 1 0 1 0 0 A0 X R/W
X = Don't Care
START CONDITION 1 2
CLOCK PULSE FOR ACKNOWLEDGE 8 9
SCL
SDA BY TRANSMITTER
S SDA BY RECEIVER
Figure 6. Acknowledge
SDA
1
0
1
0
A1
A0
X
R/W
ACK
START
MSB
LSB
SCL
Figure 7. Slave Address 32 ______________________________________________________________________________________
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Send Byte The send byte protocol allows the master device to send one byte of data to the slave device (see Figure 8). The send byte presets a register pointer address for a subsequent read or write. The slave sends a NACK instead of an ACK if the master tries to send an address that is not allowed or if the device is writing data to EEPROM or is booting. If the master sends C0h, the data is ACK. This could be the start of the block write protocol, and the slave expects the following data bytes. If the master sends a Stop condition, the internal address pointer does not change. If the master sends C1h, this signifies that the block read protocol is expected, and a repeated Start condition should follow. The device reboots if the master sends C4h. The send byte procedure follows: 1) The master sends a Start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit data byte. 5) The addressed slave asserts an ACK on SDA. 6) The master sends a Stop condition. Write Byte The write byte protocol allows the master device to write a single byte in the register bank or in the EEPROM (configuration or user) (see Figure 8). The Write Byte procedure follows: 1) The master sends a Start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit command code. 5) The addressed slave asserts an ACK on SDA. 6) The master sends an 8-bit data byte. 7) The addressed slave asserts an ACK on SDA. 8) The master sends a Stop condition. In order to write a single byte to the register bank, only the 8-bit command code and a single 8-bit data byte are sent. The command code must be in the range of 00h to 2Eh. The data byte is written to the register bank if the command code is valid. The slave generates a NACK at step 5 if the command code is invalid or any internal operations are ongoing. In order to write a single byte of data to the user or configuration EEPROM, the 8-bit command code and a single 8-bit data byte are sent. The following 8-bit data byte is written to the addressed EEPROM location. Block Write The block write protocol allows the master device to write a block of data (1 to 16 bytes) to the EEPROM or to the register bank (see Figure 8). The destination address must already be set by the send byte protocol and the command code must be C0h. If the number of bytes to be written causes the address pointer to exceed 2Fh for the configuration register or B7h for the configuration EEPROM, the address pointer stops incrementing, overwriting the last memory address with the remaining bytes of data. Only the last data byte sent is stored in B7h (as 2Fh is read only and a write causes no change in the content). If the number of bytes to be written exceeds the address pointer 7Fh for the user EEPROM, the address pointer stops incrementing and continues writing exceeding data to the last address. Only the last data is actually written to 7Fh. The block write procedure follows: 1) The master sends a Start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends the 8-bit command code for block write (C0h). 5) The addressed slave asserts an ACK on SDA. 6) The master sends the 8-bit byte count (1 to 16 bytes) N. 7) The addressed slave asserts an ACK on SDA. 8) The master sends 8 bits of data. 9) The addressed slave asserts an ACK on SDA. 10) Repeat steps 8 and 9 N - 1 times. 11) The master generates a Stop condition.
MAX6889/MAX6890/MAX6891
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EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Read Byte The read byte protocol allows the master device to read the register or an EEPROM location (user or configuration) content of the MAX6889/MAX6890/MAX6891 (see Figure 8). The read byte procedure follows: 1) The master sends a Start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on the data line. 4) The master sends 8 data bits. 5) The active slave asserts an ACK on the data line. 6) The master sends a repeated Start condition. 7) The master sends the 7-bit slave ID plus a read bit (high). 8) The addressed slave asserts an ACK on the data line. 9) The slave sends 8 data bits. 10) The master asserts a NACK on the data line 11) The master generates a Stop condition. Note that once the read has been done, the internal pointer is increased by one, unless a memory boundary is hit. If the device is busy or if the address is not an allowed one, the command code is NACKed and the internal address pointer is not altered. The master must then interrupt the communication issuing a STOP condition. Block Read The block read protocol allows the master device to read a block of 16 bytes from the EEPROM or register bank (see Figure 8). Read fewer than 16 bytes of data by issuing an early STOP condition from the master, or by generating a NACK with the master. Previous actions through the serial interface predetermines the first source address. It is suggested to use a send byte protocol, before the block read, to set the initial read address. The block read protocol is initiated with a command code of C1h. The block read procedure follows: 1) The master sends a Start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends 8 bits of the block read command (C1h). 5) The slave asserts an ACK on SDA, unless busy. 6) The master generates a repeated Start condition. 7) The master sends the 7-bit slave address and a read bit (high). 8) The slave asserts an ACK on SDA. 9) The slave sends the 8-bit byte count (16). 10) The master asserts an ACK on SDA. 11) The slave sends 8 bits of data. 12) The master asserts an ACK on SDA. 13) Repeat steps 8 and 9 15 times. 14) The master generates a Stop condition. Address Pointers Use the send byte protocol to set the register address pointers before read and write operations. For the configuration registers, valid address pointers range from 00h to 2Fh. Register addresses outside of this range result in a NACK being issued from the MAX6889/ MAX6890/MAX6891. When using the block write protocol, the address pointer automatically increments after each data byte, except when the address pointer is already at 2Fh. If the address pointer is already 2Fh, and more data bytes are being sent, these subsequent bytes overwrite address 2Fh repeatedly. No data will be left in 2Fh as this is a read-only address. For the configuration EEPROM, valid address pointers range from 80h to B7h (even if they are only meaningful up to AEh). When using the block write protocol, the address pointer automatically increments after each data byte, except when the address pointer is already at B7h. If the address pointer is already B7h, and more data bytes are being sent, these subsequent bytes overwrite address B7h repeatedly, leaving only the last sent data byte stored at this register address. For the user EEPROM, valid address pointers range from 40h to 7Fh. As for the configuration EEPROM, block write and block read protocols can also be used. The internal address pointer will auto-increment up to the user-EEPROM boundary 7Fh where the pointer will stop incrementing. When writing, only the last data written will be stored in 7Fh.
34
______________________________________________________________________________________
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891 MAX6889/MAX6890/MAX6891 MAX6889/MAX6890/MAX6891 MAX6889/MAX6890/MAX6891 MAX6889/MAX6890/MAX6891 MAX6889/MAX6890/MAX6891 MAX6889/MAX6890/MAX6891
SEND BYTE FORMAT S ADDRESS 7 bits WR 0 ACK DATA 8 bits Data Byte-presets the internal address pointer or represents a command. ACK P READ BYTE FORMAT S ADDRESS 7 bits Slave Address- equivalent to chipselect line of a 3-wire interface. WR 0 ACK DATA 8 bits Data Byte--presets the internal address pointer. ACK SR ADDRESS 7 bits Slave Address-- equivalent to chipselect line of a 3-wire interface. WR 1 ACK DATA 8 bits Data Byte-data read from the preset register (or EEPROM) address. ACK P
Slave Address- equivalent to chipselect line of a 3wire interface. WRITE BYTE FORMAT S ADDRESS 7 bits Slave Address- equivalent to chipselect line of a 3wire interface. WR 0
ACK
COMMAND 8 bits
ACK
DATA 8 bits
ACK
P
Command Byte- selects register EEPROM location you are writing to.
Data Byte-data goes into the register (or EEPROM location) set by the command byte.
BLOCK WRITE FORMAT S ADDRESS 7 bits Slave Address- equivalent to chipselect line of a 3wire interface. BLOCK READ FORMAT S ADDRESS 7 bits WR 0 ACK COMMAND C1h Command Byte- prepares device for block operation. ACK SR ADDRESS 7 bits WR 1 ACK BYTE COUNT = N 8 bits ACK DATA BYTE ACK 1 8 bits DATA BYTE ... 8 bits ACK DATA BYTE ACK N 8 bits P WR 0 ACK COMMAND ACK C0h Command Byte- prepares device for block write operation. BYTE COUNT= N 8 bits ACK DATA BYTE 1 8 bits ACK DATA BYTE ... 8 bits ACK DATA BYTE N 8 bits ACK P
Data Byte-first data goes into the address preset with a previous "Set Address" and the following data in the following locations.
Slave Address- equivalent to chipselect line of a 3wire interface.
Slave Address- equivalent to chipselect line of a 3wire interface.
Data Byte-data comes from the address set by a previous "send byte".
S = Start condition. P = Stop condition.
Shaded = Slave transmission. SR = Repeated start condition.
Figure 8. SMBus/I2C Protocols
Applications Information
Configuration Download at Power-up
The configuration of the MAX6889/MAX6890/MAX6891 (undervoltage thresholds, PO_ timeout periods, watchdog behavior, programmable output conditions and configurations, etc.) depends on the contents of the EEPROM. The EEPROM is comprised of buffered latches that store the configuration. The local volatile memory latches lose their contents at power-down. Therefore, at power-up, the device configuration must be restored by downloading the contents of the EEPROM (non-
volatile memory) to the local latches. This download occurs in a number of steps: 1) Programmable outputs go high impedance with no power applied to the device. 2) When VCC exceeds 1V, all programmable outputs are weakly pulled to GND through a 10A current sink. 3) When V CC exceeds UVLO, the configuration EEPROM starts to download its contents to the volatile configuration registers. The programmable outputs assume their programmed conditional output state when VCC exceeds UVLO.
35
______________________________________________________________________________________
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
4) Any attempt to communicate with the device prior to this download completion results in a NACK being issued from the MAX6889/MAX6890/MAX6891. Other Fault Signals from C Connect a general-purpose output from a C to one of the GPI_ inputs to allow interrupts to assert any output of the MAX6889/MAX6890/MAX6891. Configure one of the programmable outputs to assert on whichever GPI_ input connects to the general-purpose output of the C.
Forcing Programmable Outputs High During Power-up
A weak, 10A pulldown current holds all programmable outputs low during power-up until V CC exceeds the undervoltage-lockout (UVLO) threshold. Applications requiring a guaranteed high programmable output for VCC down to GND require external pullup resistors to maintain the logic state until VCC exceeds UVLO. Use 20k resistors for most applications.
Layout and Bypassing
For better noise immunity, bypass each of the voltage detector inputs to GND with 0.1F capacitors installed as close to the device as possible. Bypass V CC and DBP to GND with 1F capacitors installed as close to the device as possible. VCC (when not externally supplied) and DBP are internally generated voltages and should not be used to supply power to external circuitry.
Uses for General-Purpose Inputs (GPI_)
Watchdog Timer Program GPI_ as an input to the watchdog timer in the MAX6889/MAX6890/MAX6891. The GPI_ input must toggle within the watchdog timeout period; otherwise any programmable output dependent on the watchdog timer will assert. Additional Manual Reset Functions The programmable outputs allow a set of conditions to assert the output. Program the set of conditions to depend on one of the GPI_ inputs. Any output that depends on GPI_ asserts when GPI_ is held in its active state, effectively acting as a manual reset input.
Configuration Latency Period
A delay of less than 5s occurs between writing to the configuration registers and the time when these changes actually take place, unless when changing one of the voltage detector's thresholds. Changing a voltage detector threshold typically takes 150s. When changing EEPROM contents, a software reboot or cycling of power is required for these changes to transfer to volatile memory.
Chip Information
PROCESS: BiCMOS
Register Map
REGISTER ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh EEPROM MEMORY ADDRESS 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh READ/ WRITE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION IN1 undervoltage detector threshold (Table 2) IN2 undervoltage detector threshold (Table 3) IN3 undervoltage detector threshold (Table 3) IN4 undervoltage detector threshold (Table 3) IN5 undervoltage detector threshold (MAX6889/MAX6890 only) (Table 3) IN6 undervoltage detector threshold (MAX6889/MAX6890 only) (Table 3) IN7 undervoltage detector threshold (MAX6889 only) (Table 3) IN8 undervoltage detector threshold (MAX6889 only) (Table 4) Threshold range selection (Tables 2, 3, and 4) High-Z mode selection (Tables 2, 3, and 4) PO1 input selection (Table 7) PO1 input selection (Table 7) PO1 timeout period, programmable output polarity, and output type selection (Tables 17, 18, and 19) PO2 input selection (Table 8) PO2 input selection (Table 8)
36
______________________________________________________________________________________
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Register Map (continued)
REGISTER ADDRESS 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh EEPROM MEMORY ADDRESS 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh READ/ WRITE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W R/W DESCRIPTION PO2 timeout period and output type selection (Tables 17, 18, and 19) PO3 input selection (Table 9) PO3 input selection (Table 9) PO3 timeout period and output type selection (Tables 17, 18, and 19) PO4 input selection (Table 10) PO4 input selection (Table 10) PO4 timeout period and output type selection (Tables 17, 18, and 19) PO5 input selection (Table 11) PO5 input selection (Table 11) PO5 timeout period and output type selection (Tables 17, 18, and 19) PO6 (MAX6889/MAX6890) input selection (Table 12) PO6 (MAX6889/MAX6890) input selection (Table 12) PO6 (MAX6889/MAX6890) timeout period and output type selection (Tables 17, 18, and 19) PO7 (MAX6889/MAX6890) input selection (Table 13) PO7 (MAX6889/MAX6890) input selection (Table 13) PO7 (MAX6889/MAX6890) timeout period and output type selection (Tables 17, 18, and 19) PO8 (MAX6889/MAX6890) input selection (Table 14) PO8 (MAX6889/MAX6890) input selection (Table 14) PO8 (MAX6889/MAX6890) timeout period and output type selection (Tables 17, 18, and 19) PO9 (MAX6889 only) input selection (Table 15) PO9 (MAX6889 only) input selection (Table 15) PO9 (MAX6889 only) timeout period and output type selection (Tables 17, 18, and 19) PO10 (MAX6889 only) input selection (Table 16) PO10 (MAX6889 only) input selection (Table 16) PO10 (MAX6889 only) timeout period and output type selection (Tables 17, 18, and 19) GPI_ input polarity selection WD input selection and clear dependency (Table 20) WD initial and normal timeout duration and disable (Table 21) Reserved. Should not be overwritten. User EEPROM write disable (Table 23) User EEPROM write disable (Table 23) Configuration lock and internal/external VCC power (Table 22)
______________________________________________________________________________________
37
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Pin Configurations
PO1 N.C.
PO1
N.C.
IN1
IN4
23
IN2
IN1
IN4
IN2
IN3
32
PO2 PO3 PO4 GND PO5 PO6 PO7 PO8
31
30
29
28
27
26
IN5
25 24 23 22 21
IN7 IN8 DBP PO4 3 4 5 6 7 PO2 PO3 1 2
IN6
28
27
26
25
24
IN3
22 21 20 19 IN6 DBP VCC GPI1 GPI2 GPI3 GPI4
1 2 3 4 5 6 7 8 9
PO9
VCC GPI1 GPI2 GPI3 GPI4 GND PO5 PO6 PO7
IN5
TOP VIEW
TOP VIEW
MAX6889
20 19 18
MAX6890
18 17 16
*EXPOSED PAD 10
PO10
17 13
SDA
*EXPOSED PAD 8 9 10 11 12 13 14
15
11
MARGIN
12
MR
14
SCL
15
A0
16
A1
MARGIN
PO8
MR
SDA
A0
(5mm x 5mm THIN QFN)
*EXPOSED PAD INTERNALLY CONNECTED TO GND.
(5mm x 5mm THIN QFN)
*EXPOSED PAD INTERNALLY CONNECTED TO GND.
PO1
TOP VIEW
IN1
20
19
18
IN2
17
IN3
16
IN4
PO2
1
15
DBP
PO3
2
14
VCC GPI1
PO4
3
MAX6891
13
GND
4
12
GPI2
PO5
5
*EXPOSED PAD 6 7 8 9 10
11
GPI3
SDA
SCL
*EXPOSED PAD INTERNALLY CONNECTED TO GND.
38
______________________________________________________________________________________
MARGIN
(5mm x 5mm THIN QFN)
MR
A0
SCL
A1
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
Typical Operating Circuit
12V DC-DC 1 DC-DC 2 DC-DC 3 12V 5V 3.3V 2.5V
MAX6889/MAX6890/MAX6891
RPU IN1 MARGIN MR VCC PO1 IN2 PO2 IN3 PO3 IN4 SDA SCL PO4
RPU P SDA SCL RESET NMI, WD ALERT LOGIC OUTPUT
MAX6891
DBP GND GPI2 GPI3
PO5 GPI1 (WD) A0
12V SUPPLY PO1 5V SUPPLY PO2 2.5V SUPPLY PO3 3.3V SUPPLY PO4 tPO1
12V BUS INPUT ENABLE 5V DC-DC CONVERTER 5V OUTPUT tPO2 ENABLE 2.5V DC-DC CONVERTER 2.5V OUTPUT tPO3 ENABLE 3.3V DC-DC CONVERTER 3.3V OUTPUT tPO4 SYSTEM RESET
______________________________________________________________________________________
39
EEPROM-Programmable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6889/MAX6890/MAX6891
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
L
D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e
C L C L
b D2/2
0.10 M C A B
XXXXX
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
G
1
2
COMMON DIMENSIONS PKG. 20L 5x5 28L 5x5 32L 5x5 16L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1
EXPOSED PAD VARIATIONS
D2
MIN. NOM. MAX. MIN.
E2
NOM. MAX.
L
0.15
DOWN BONDS ALLOWED
3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.25 - 0.25 - 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 -
** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** **
NO YES NO NO YES NO Y NO NO YES YES NO NO YES Y N NO YES NO NO
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
** SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
G
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
40 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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